An All-Digital PLL Using Random Modulation for SSC Generation in 65nm CMOS

被引：0
|
作者：
Da Dalt, Nicola [1 ]
Pridnig, Peter [1 ]
Grollitsch, Werner [1 ]
机构：
[1] Infineon Technol, Villach, Austria
来源：
2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC) | 2013年 / 56卷
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：252 / +
页数：3
相关论文
共 50 条
  • [1] An All-Digital PLL Synthesized from a Digital Standard Cell Library in 65nm CMOS
    Park, Youngmin
    Wentzloff, David D.
    [J]. 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2011,
  • [2] An All-Digital PLL with SAR Frequency Locking System in 65nm SOTB CMOS
    Arai, Keita
    Pham, Cong-Kha
    [J]. 2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2016,
  • [3] A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLL in 65nm CMOS
    Wu, Wanghua
    Bai, Xuefei
    Staszewski, Robert Bogdan
    Long, John R.
    [J]. 2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 352 - +
  • [4] An All-Digital On-Chip Jitter Measurement Circuit in 65nm CMOS technology
    Chung, Ching-Che
    Chu, Wei-Jung
    [J]. 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2011, : 179 - 182
  • [5] Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS
    Staszewski, Robert Bogdan
    Waheed, Khurram
    Duelger, Fikret
    Eliezer, Oren E.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (12) : 2904 - 2919
  • [6] A 50-to-66GHz 65nm CMOS All-Digital Fractional-N PLL with 220fsrms Jitter
    Hussein, Ahmed
    Vasadi, Sriharsha
    Soliman, Mazen
    Paramesh, Jeyanandh
    [J]. 2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 326 - 326
  • [7] Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
    Biereigel, Stefan
    Kulis, Szymon
    Moreira, Paulo
    Kolpin, Alexander
    Leroux, Paul
    Prinzie, Jeffrey
    [J]. ELECTRONICS, 2021, 10 (22)
  • [8] An All-digital PLL for Satellite Based Navigation in 90 nm CMOS
    Neyer, Andreas
    Wunderlich, Ralf
    Heinen, Stefan
    [J]. 2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2009, : 41 - 44
  • [9] A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS Technology
    Chung, Ching-Che
    Chang, Chia-Lin
    [J]. 2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 66 - 69
  • [10] An All-Digital Clock and Data Recovery Circuit for Spread Spectrum Clocking Applications in 65nm CMOS Technology
    Chung, Ching-Che
    Sheng, Duo
    Lin, Yang-Di
    [J]. 2012 4TH ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ASQED), 2012, : 91 - 94
12345