Architecture for multi-processor SoC platform using dedicated channels

被引：0
|
作者：
Lee, G
Park, SC
机构：
来源：
Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A multi-processor architecture for the platform based SoC design is proposed. Dedicated FIFOs are selected as channels between processors for designing of wireless communication system. The conditions to meet the latency and the throughput requirements are also proposed with generalized equations. To demonstrate the suggested equations, an 802.11a system is analyzed. They are confirmed by simulation of SystemC transaction level modeling..
引用
收藏
页码：525 / 529
页数：5
相关论文
共 50 条
  • [1] Case study : System level design for architecture exploration of multi-processor based SoC platform
    Yoon, Sung-Rok
    Park, Sin-Chong
    [J]. 2006 8TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, VOLS 1-4, 2006, : 3154 - 3157
  • [2] A generic wrapper architecture for multi-processor SoC cosimulation and design
    Yoo, S
    Nicolescu, G
    Lyonnard, D
    Baghdadi, A
    Jerraya, AA
    [J]. PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN, 2001, : 195 - 200
  • [3] Multi-Processor Debug in SoC and Processor designs
    Penner, Bill
    [J]. 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [4] Application of a multi-processor SoC platform to high-speed packet forwarding
    Paulin, PG
    Pilkington, C
    [J]. DESIGNERS' FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2004, : 58 - 63
  • [5] A reconfigurable network-on-chip architecture for optimal multi-processor SoC communication
    Rana V.
    Atienza D.
    Santambrogio M.D.
    Sciuto D.
    De Micheli G.
    [J]. IFIP Advances in Information and Communication Technology, 2010, 313 : 232 - 250
  • [6] A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication
    Rana, Vincenzo
    Atienza, David
    Santambrogio, Marco Domenico
    Sciuto, Donatella
    De Micheli, Giovanni
    [J]. VLSI-SOC: DESIGN METHODOLOGIES FOR SOC AND SIP, 2010, 313 : 232 - +
  • [7] A Reconfigurable Multi-Processor SoC for Media Applications
    Zhu, Min
    Liu, Leibo
    Yin, Shouyi
    Wang, Yansheng
    Wang, Wenjie
    Wei, Shaojun
    [J]. 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 2011 - 2014
  • [8] Adaptive dynamic arbiter for multi-processor SoC
    Xu, Yi
    Li, Li
    Du, Gaoming
    Zhang, Yuang
    Zhang, Bing
    Gao, Minglun
    [J]. Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2008, 45 (06): : 1085 - 1092
  • [9] SoC platform architecture for a network processor
    Ghattas, H
    Mbaye, M
    Bissou, JP
    Savaria, Y
    [J]. INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2003, : 49 - 52
  • [10] A multi-processor platform for signal processing
    Freeman, BJ
    [J]. SIGNAL PROCESSING, SENSOR FUSION, AND TARGET RECOGNITION VII, 1998, 3374 : 483 - 494
12345