SystemG-based reconfigurable IP modelling for system-on-chip design

被引：0

作者：

Ahmadinia, Ali ^{[1
]}

Ahmad, Balal ^{[1
]}

Erdogan, Ahmet ^{[1
]}

Arslan, Tughrul ^{[1
]}

机构：

[1] Univ Edinburgh, Sch Engn & Elect, Edinburgh EH9 3JL, Midlothian, Scotland

来源：

PROCEEDINGS OF THE 2008 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS | 2008年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different runtime periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and plugged into a LEON platform for co-simulation.

引用

页码：362 / 367

页数：6

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