A 0.55 V 7-bit 160 MS/s Interpolated Pipeline ADC Using Dynamic Amplifiers

被引：0
|
作者：
Lin, James [1 ]
Paik, Daehwa [1 ]
Lee, Seungjong [1 ]
Miyahara, Masaya [1 ]
Matsuzawa, Akira [1 ]
机构：
[1] Tokyo Inst Technol, Dept Phys Elect, Meguro Ku, Tokyo 1528552, Japan
来源：
2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2013年
关键词：
FLASH ADC; COMPARATOR;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a 0.55 V, 7-bit, 160 MS/s pipeline ADC using dynamic amplifiers. In this ADC, dynamic amplifiers with a common-mode detection technique are used as residual amplifiers to increase its robustness against supply voltage lowering. These amplifiers also remove the unnecessary static power consumption achieving clock-scalability in power performance. The 7-bit prototype ADC fabricated in 90 nm CMOS demonstrates an ENOB of 6.0 bits at a conversion rate of 160 MS/s with an input close to the Nyquist frequency. At this conversion rate, it consumes 2.43 mW from a 0.55 V supply. The resulting FoM is 240 fJ/c.-s.
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页数：4
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