Pipeline and Parallel Processor Architecture for Fast Computation of 3D-DWT using Modified Lifting Scheme

A pipelined parallel processing 3D DWT architecture is designed in this paper based on lifting scheme algorithm with 9/7 wavelet filters. The 3D DWT architecture process a 512x512 image with 8 groups of frames sequentially with improved throughput. The first stage computes 1D-DWT along the rows with 4 parallel processors, the memory interface with FIFO reduces latency between first stage and second stage that computes 2D DWT computation. 3D DWT computes wavelet coefficients in the temporal direction and designed to operate from 512*4 clock cycles in sequence along with 1D and 2D DWT computation. The FIFO designed synchronizes the data movement. Memories at every stage are designed to store the parallel processed data. The proposed architecture has high performance and is suitable for high speed, low power and portable applications. With utilization of 51% of slice registers 3D-DWT architecture implemented on Virtex-5 FPGA and frequency of operation is 373 MHz. The designed DWT-IDWT can be used as IP Core.