A self-checking cell logic block for fault tolerant FPGAs

被引：0

作者：

Pontarelli, S ^{[1
]}

Cardarilli, GC ^{[1
]}

Leandri, A ^{[1
]}

Ottavi, M ^{[1
]}

Re, M ^{[1
]}

Salsano, A ^{[1
]}

机构：

[1] Univ Roma Tor Vergata, Dept Elect Engn, I-00133 Rome, Italy

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-Up-Table (LUT) and a D Flip-Flop. The CLB is designed using pass-transistor-based multiplexers, either to select the output of the 4-input LUT or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a sensor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection of any single transistor fault.

引用

页码：477 / 480

页数：4

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