An integrated design approach for self-checking FPGAs

被引：8
|
作者：
Bolchini, C [1 ]
Salice, F [1 ]
Sciuto, D [1 ]
Zavaglia, R [1 ]
机构：
[1] Politecn Milan, Dipartimento Elettron & Informat, I-20133 Milan, Italy
来源：
18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/DFTVS.2003.1250142
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes a methodology for designing FPGAs able to self-detect the occurrence of hardware failures, integrated in a standard, industrial design flow. The approach improves the results proposed in the past, by defining a testing environment which takes into account the peculiarities of FPGA platforms.
引用
收藏
页码：443 / 450
页数：8
相关论文
共 50 条
  • [1] A technique for designing self-checking logic for FPGAS
    Lala, PK
    Burress, AL
    [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI, 1999, : 94 - 96
  • [2] Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs
    Kanno, Yusuke
    Toba, Tadanobu
    Shimamura, Kotaro
    Kanekawa, Nobuyasu
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (03) : 726 - 735
  • [3] DESIGN APPROACH TO SELF-CHECKING PROCESSORS.
    Nanya, Takashi
    Kawamura, Toshiaki
    [J]. Systems and Computers in Japan, 1986, 17 (10): : 20 - 33
  • [4] Approach to partially self-checking combinational circuits design
    Djordjevic, GL
    Stojcev, MK
    Stankovic, TR
    [J]. MICROELECTRONICS JOURNAL, 2004, 35 (12) : 945 - 952
  • [5] Designing self-checking FPGAs through error detection codes
    Bolchini, C
    Salice, F
    Sciuto, D
    [J]. 17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2002, : 60 - 68
  • [6] A fine grain configurable logic block for self-checking FPGAs
    Lala, PK
    Walker, A
    [J]. VLSI DESIGN, 2001, 12 (04) : 527 - 536
  • [7] A self-checking cell logic block for fault tolerant FPGAs
    Pontarelli, S
    Cardarilli, GC
    Leandri, A
    Ottavi, M
    Re, M
    Salsano, A
    [J]. 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS, 2002, : 477 - 480
  • [8] Approach to partially self-checking finite state machine design
    Djordjevic, G. Lj.
    Stankovic, T. R.
    Stojcev, M. K.
    [J]. 2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2006, : 697 - +
  • [9] DESIGN OF A SELF-CHECKING MICROPROGRAM CONTROL
    COOK, RW
    SISSON, WH
    STOREY, TF
    TOY, WN
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1973, C 22 (03) : 255 - 262
  • [10] Self-checking microprogrammed controller design
    Lala, PK
    Walker, A
    [J]. ICEMI'99: FOURTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1 AND 2, CONFERENCE PROCEEDINGS, 1999, : 555 - 559
12345