Self-checking logic arrays

被引:0
|
作者
机构
[1] Nicolaidis, M.
[2] Courtois, B.
来源
Nicolaidis, M. | 1600年 / 13期
关键词
Fault/Error Modelling - Microsystems - Programmable Logic Arrays (PLA) - RAM - ROM - Self-Checking Logic Arrays;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [1] SELF-CHECKING LOGIC-ARRAYS
    NICOLAIDIS, M
    COURTOIS, B
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 1989, 13 (04) : 281 - 290
  • [2] SELF-CHECKING COMBINATIONAL LOGIC BINARY COUNTERS
    DORR, RC
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1972, C 21 (12) : 1426 - 1430
  • [3] A technique for designing self-checking logic for FPGAS
    Lala, PK
    Burress, AL
    [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI, 1999, : 94 - 96
  • [4] SELF-CHECKING PROCESSING ELEMENTS IN CELLULAR ARRAYS
    TOTH, N
    [J]. LECTURE NOTES IN COMPUTER SCIENCE, 1989, 342 : 353 - 359
  • [5] Self-checking logic design for FPGA implementation
    Lala, PK
    Burress, AL
    [J]. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2003, 52 (05) : 1391 - 1398
  • [6] SELF-CHECKING LOGIC FLAGS ERRORS AS THEY HAPPEN
    LALA, PK
    [J]. EDN, 1993, 38 (01) : 73 - &
  • [7] VHDL description of self-checking logic circuits
    Busaba, FY
    [J]. PROCEEDINGS OF THE TWENTY-EIGHTH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY, 1996, : 477 - 481
  • [8] A fine grain configurable logic block for self-checking FPGAs
    Lala, PK
    Walker, A
    [J]. VLSI DESIGN, 2001, 12 (04) : 527 - 536
  • [9] A technique for designing totally self-checking domino logic circuits
    Tang, CK
    Lala, PK
    Parkerson, JP
    [J]. 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 128 - 132
  • [10] A self-checking cell logic block for fault tolerant FPGAs
    Pontarelli, S
    Cardarilli, GC
    Leandri, A
    Ottavi, M
    Re, M
    Salsano, A
    [J]. 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS, 2002, : 477 - 480