Self-checking logic design for FPGA implementation

Field programmable gate arrays (FPGAs) are being increasingly used in many systems including intelligent instrumentation. A synthesis algorithm for generating self-checking combinational logic for implementation on look-up table based FPGAs is presented. The algorithm maps Boolean functions into FPGAs such that self-checking features are automatically incorporated into designs, allowing on-line detection of faults in the combinational function block within any CLB of an FPGA and on the interconnect lines that connect these blocks. This is accomplished by utilizing two types of cells, a functional cell and a checker cell, that generate complementary outputs during normal operation, and outputs of the same value in the presence of a fault. If a fault occurs in any intermediate functional cell, it is automatically propagated to the primary outputs. A checker cell is then used to verify the correctness of the final outputs, thus allowing self-checking.