System-level power/performance analysis for embedded systems design

被引:0
|
作者
Nandi, A [1 ]
Marculescu, R [1 ]
机构
[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA
关键词
platform-based design; system-level analysis; stochastic automata networks; multimedia systems;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a formal technique for system level power/performance analysis that can help the designer to select the right platform starting from a set of target applications. By platform we mean a family of heterogeneous architectures that satisfy a set of architectural constraints imposed to allow re-use of hardware and software components. More precisely, we introduce the Stochastic Automata Networks (SANs) as an effective formalism for average-case analysis that can be used early in the design cycle to identify the best power/performance figure among several application-architecture combinations. This information not only helps avoid lengthy profiling simulations, but also enables efficient mappings of the applications onto the chosen platform. We illustrate the features of our technique through the design of an MPEG-2 video decoder application.
引用
收藏
页码:599 / 604
页数:6
相关论文
共 50 条
  • [21] A Co-simulation Approach for System-Level Analysis of Embedded Control Systems
    Glass, Michael
    Teich, Juergen
    Zhang, Liyuan
    [J]. 2012 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS (SAMOS): ARCHITECTURES, MODELING AND SIMULATION, 2012, : 355 - 362
  • [22] Search-space Decomposition for System-level Design Space Exploration of Embedded Systems
    Richthammer, Valentina
    Fassnacht, Fabian
    Glass, Michael
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2020, 25 (02)
  • [23] A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems
    Ascia, Giuseppe
    Catania, Vincenzo
    Palesi, Maurizio
    Patti, Davide
    [J]. ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 940 - 943
  • [24] System-level performance analysis in SystemC
    Posadas, H
    Herrera, F
    Sánchez, P
    Villar, E
    Blasco, F
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 378 - 383
  • [25] RISC VLSI DESIGN FOR SYSTEM-LEVEL PERFORMANCE
    ROWEN, C
    CRUDELE, L
    FREITAS, D
    HANSEN, C
    HUDSON, E
    KINSEL, J
    MOUSSOURIS, J
    PRZYBYLSKI, S
    RIORDAN, T
    [J]. VLSI SYSTEMS DESIGN, 1986, 7 (03): : 81 - &
  • [26] System-level performance analysis of embedded system using behavioral C/C++ model
    Chung, MK
    Na, S
    Kyung, CM
    [J]. 2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION & TEST (VLSI-TSA-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 188 - 191
  • [27] Massive MIMO Uplink Scheme Design and System-Level Performance Analysis
    Li, Yang
    Wang, Rui
    Tan, Haisheng
    Chen, Yifan
    Zhang, Qingfeng
    [J]. IEEE ACCESS, 2018, 6 : 3212 - 3230
  • [28] Power-performance system-level exploration of a MicroSPARC2-based embedded architecture
    Palermo, G
    Silvano, C
    Zaccaria, V
    [J]. DESIGNERS FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2003, : 182 - 187
  • [29] Reliability-Driven System-Level Synthesis of Embedded Systems
    Bolchini, Cristiana
    Miele, Antonio
    [J]. 2010 IEEE 25TH INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS (DFT 2010), 2010, : 35 - 43
  • [30] Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
    Atienza, D
    Mamagkakis, S
    Poletti, F
    Mendias, JM
    Catthoor, F
    Benini, L
    Soudris, D
    [J]. INTEGRATION-THE VLSI JOURNAL, 2006, 39 (02) : 113 - 130