Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell

被引：0
|
作者：
Woo, Youngtag [1 ]
Ichihashi, Motoi [1 ]
Parihar, Sanjay [1 ]
Yuan, Lei [1 ]
Banna, Srinivasa [1 ]
Kye, Jongwook [1 ]
机构：
[1] GLOBALFOUNDRIES, 2600 Great Amer Way, Santa Clara, CA 95054 USA
来源：
2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2015年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页数：4
相关论文
共 50 条
  • [31] Design Technology Co-optimization (DTCO) Study on Self-AlignedV-ia (SAV) with Lamella DSA for sub-7 nm Technology
    Ma, Yuansheng
    Kye, Jongwook
    Khaira, Gurdaman S.
    Hong, Le
    Word, James
    Sun, Yuyang
    Mitra, Joydeep
    Torres, J. Andres
    Fenger, Germain
    Levinson, Harry J.
    DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XI, 2017, 10148
  • [32] A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology
    Chen, Wen-Chieh
    Chen, Shih-Hung
    Huang, Man-Ching
    Chang, Shu-Wei
    Hellings, Geert
    Groeseneken, Guido
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2025, 60 (02) : 615 - 625
  • [33] Process-Design Co-Optimization for FPGA
    Xiang, Qi
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 2031 - 2034
  • [34] Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology
    Lee, Dohyeon
    Hwang, Heecheol
    Oh, Hyunteck
    Ban, Yongchan
    18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021), 2021, : 163 - 164
  • [35] Design and Process Co-optimization for 28nm/22nm and Beyond - A Foundry's Perspective
    Hou, Cliff
    2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 418 - 418
  • [36] Ab Initio for Design-Technology Co-Optimization
    Aboud, Shela J.
    Huang, Joanne
    Cobb, Jonathan
    Gunst, Tue
    Asenov, Plamen
    Dam, Thuc
    Borges, Ricardo
    DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION XV, 2021, 11614
  • [37] Design-Patterning Co-optimization of SRAM Robustness for Double Patterning Lithography
    Joshi, Vivek
    Agarwal, Kanak
    Sylvester, Dennis
    2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2012, : 713 - 718
  • [38] Design and Manufacturing Process Co-optimization in Nano-Technology (Designer Track Paper)
    Hsu, Meng-Kai
    Katta, Nitesh
    Lin, Homer Yen-Hung
    Lin, Keny Tzu-Hen
    Tam, King Ho
    Wang, Ken Chung-Hsing
    2014 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2014, : 574 - 581
  • [39] Design-Technology Co-Optimization of Sequential and Monolithic CFET as enabler of technology node beyond 2nm
    Chehab, Bilal
    Ryckaert, Julien
    Schuddinck, Pieter
    Weckx, Pieter
    Horiguchi, Naoto
    Mirabelli, Gioele
    Spessot, Alessio
    Na, Myunghee
    DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION XV, 2021, 11614
  • [40] Design-Technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET Technology
    Chao, Yu-Lin
    Kulkarni, Sarvesh H.
    Cha, Soonwoo
    Paulson, Leif R.
    Rajarshi, Salil M.
    Bloomstrom, Jason
    Liu, Guannan
    Armstrong, Mark
    Li, Jiabo
    Su, Chen-Yi
    Ramey, Stephen M.
    Bhattacharya, Uddalak
    Sell, Bernhard
    Zhang, Ying
    2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
12345