Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell

被引：0
|
作者：
Woo, Youngtag [1 ]
Ichihashi, Motoi [1 ]
Parihar, Sanjay [1 ]
Yuan, Lei [1 ]
Banna, Srinivasa [1 ]
Kye, Jongwook [1 ]
机构：
[1] GLOBALFOUNDRIES, 2600 Great Amer Way, Santa Clara, CA 95054 USA
来源：
2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2015年
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
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页数：4
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