Survey of low power techniques for VLSI design

被引：2
|
作者：
deAngel, E
Swartzlander, EE
机构：
来源：
EIGHTH ANNUAL IEEE INTERNATIONAL CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON, 1996 PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/ICISS.1996.552423
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 mu m technology and simulated in PowerMill.
引用
收藏
页码：159 / 169
页数：11
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