Low Power Asynchronous Circuit Design Methodology using a new Single Gate Sleep Convention Logic (SG-SCL)

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. 4x4 multipliers have been designed in a 45nm predictive technology using the proposed SG-SCL gates and pipeline structure and using the conventional MTNCL (Safe SECRII architecture), and they have been compared in terms of speed, power consumption, energy and size. The simulation results show that the proposed design reduces 60% energy, 54% leakage power and 25% area compared to the MTNCL (Safe SECRII architecture) design.