FPGA for high-performance bit-serial pipeline datapath

被引：1

作者：

Isshiki, T ^{[1
]}

Shimizugashira, T ^{[1
]}

Ohta, A ^{[1
]}

Amril, I ^{[1
]}

Kunieda, H ^{[1
]}

机构：

[1] Tokyo Inst Technol, Meguro Ku, Tokyo 152, Japan

来源：

PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 | 1998年

关键词：

D O I：

10.1109/ASPDAC.1998.669490

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we introduce our work on the chip design of a new FPGA chip for highperformance bit-serial pipeline datapath which is customized both in the logic architecture and routing architecture. The chip consists of 200k transistors on 3.5mm square substrate (excluding the IO pad area) using 0.5 mu 2-metal process technology. The estimated clock frequency is 156MHz.

引用

页码：331 / 332

页数：2

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