Copper contact technology for sub-100nm contacts

被引:0
|
作者
Demuynck, Steven [1 ]
Zhao, Chao [1 ]
Van den Bosch, Geert [1 ]
Hinomura, Toru [1 ]
Tokei, Zsolt [1 ]
Beyer, Gerald P. [1 ]
机构
[1] IMEC, IPSI, B-3001 Louvain, Belgium
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper addresses the challenges associated with introducing a manufacturable, reliable and cost-effective Cu contact module. We show that Cu can potentially reduce the contact resistance by as much as 50% having a positive performance effect on selected devices and circuits without degrading the front-end reliability. Scalability of the PVD-based Ta(N) Cu barriers proves to be a major challenge upon implementing 65nm node compatible structures because of the need for a thick metal deposit on the contact bottom to prevent Cu silicidation. A hybrid barrier scheme with a PVD Ta bottom and ALD TaN top layer is presented as a possible route to scale Cu contact barriers beyond the 65nm technology node.
引用
下载
收藏
页码:171 / 177
页数:7
相关论文
共 50 条
  • [1] CPL mask technology for sub-100nm contact hole imaging
    Kasprowicz, BS
    Conley, W
    Litt, LC
    van den Broeke, D
    Montgomery, P
    Socha, R
    Wu, W
    Lucas, K
    Roman, B
    Chen, F
    Wampler, K
    Laidig, T
    Progler, C
    Hathorn, ME
    PHOTOMASK AND NEXT GENERATION LITHOGRAPHY MASK TECHNOLOGY XI, 2004, 5446 : 624 - 631
  • [3] Sub-100nm and deep sub-100nm MOS transistor gate patterning
    Xiang, Q
    Gupta, S
    Spence, C
    Singh, B
    Yeap, GCF
    Lin, MR
    MICROELECTRONIC DEVICE TECHNOLOGY II, 1998, 3506 : 243 - 252
  • [4] Methods to achieve sub-100nm contact hole lithography
    Lindsay, T
    Kavanagh, R
    Pohlers, G
    Kanno, T
    Bae, Y
    Barclay, G
    Kanagasabapathy, S
    Mattia, J
    ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2, 2003, 5039 : 705 - 712
  • [5] New resolution enhancement technology for manufacturing sub-100nm technology
    Chung, DH
    Park, JY
    Lee, MK
    Shin, IK
    Choi, SW
    Yoon, HS
    Sohn, JM
    Chen, F
    Van den Broeke, D
    OPTICAL MICROLITHOGRAPHY XV, PTS 1 AND 2, 2002, 4691 : 1492 - 1499
  • [6] Study on reliability of metal fuse for sub-100nm technology
    Park, D
    Hyun, CS
    Kim, HC
    Kang, HJ
    Lee, KY
    Oh, KS
    ISSM 2005: IEEE International Symposium on Semiconductor Manufacturing, Conference Proceedings, 2005, : 420 - 421
  • [7] Ultra shallow junction technology for sub-100nm CMOS
    Mizuno, B
    SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 433 - 437
  • [8] A novel resist material for sub-100nm contact hole pattern
    Chung, JH
    Choi, SJ
    Kang, Y
    Woo, SG
    Moon, JT
    ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XVII, PTS 1 AND 2, 2000, 3999 : 305 - 312
  • [9] Mask Enhancer Technology for sub-100nm Pitch Random Logic Layout Contact Hole Fabrication
    Yuito, Takashi
    Sakaue, Hiroshi
    Matsuda, Takashi
    Shimizu, Tadami
    Irie, Shigeo
    Iwamoto, Fumio
    Misaka, Akio
    Koizumi, Taichi
    Sasago, Masaru
    OPTICAL MICROLITHOGRAPHY XXIII, 2010, 7640
  • [10] SPA plasma for sub-100nm
    Murakawa, S
    Nemoto, T
    Iizuka, V
    Yamamoto, N
    Ozaki, S
    SOLID STATE TECHNOLOGY, 2003, 46 (01) : 59 - +