Evaluation of commercial ultra-thin SOI substrates using laser confocal inspection system

被引:0
|
作者
Ogura, A [1 ]
Okabayashi, O [1 ]
机构
[1] NEC Corp Ltd, Silicon Syst Res Labs, Sagamihara, Kanagawa 2291198, Japan
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Commercially available ultra-thin (50nm) SOI substrates were evaluated using a laser confocal inspection system. The defect distribution and corresponding defects were observed for both bonded SOI and SIMOX wafers. Some of the defects were marked in the system and evaluated by TEM after the samples were prepared by FIB. The most serious defects observed were voids in both the bonded Sol wafers and the SIMOX wafers. Small defects such as dislocations were also detected. The technique is non-destructive and therefore promising for use in pre- and in-line monitoring systems.
引用
收藏
页码:19 / 24
页数:6
相关论文
共 50 条
  • [41] Ultra-thin Strained-SOI CMOS for High Temperature Operation
    Maeda, T. (t-maeda@aist.go.jp), 1600, (Institute of Electrical and Electronics Engineers Inc.):
  • [42] Atomistic modeling of hole transport in ultra-thin body SOI pMOSFETs
    Minari, Hideki
    Mori, Nobuya
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2008, 7 (03) : 293 - 296
  • [43] Ultra-thin gate dielectric plasma charging damage in SOI technology
    Lai, W.
    Harmon, D.
    Hook, T.
    Ontalus, V.
    Gambino, J.
    2006 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 44TH ANNUAL, 2006, : 370 - +
  • [44] Characterization of ultra-thin SOI films for double-gate MOSFETs
    Allibert, F
    Vinet, M
    Lolivier, J
    Deleonibus, S
    Cristoloveanu, S
    2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 187 - 188
  • [45] Thermal management of ultra-thin SOI devices: Effects of phonon confinement
    Balandin, A
    Tang, YS
    Wang, KL
    SILICON-BASED OPTOELECTRONICS, 1999, 3630 : 135 - 142
  • [46] DC and Noise Characteristics of Underlap Ultra-Thin BOX SOI nMOSFETs
    Kudina, V.
    Garbar, N.
    Simoen, E.
    Claeys, C.
    2015 IEEE 35TH INTERNATIONAL CONFERENCE ON ELECTRONICS AND NANOTECHNOLOGY (ELNANO), 2015, : 119 - 123
  • [47] Evaluation of ultra-thin gate oxides using different ambients in a rapid thermal processing system
    Jia, YB
    Choi, JY
    Schuur, J
    Das, JH
    Sharangpani, R
    Thakur, RPS
    ADVANCES IN RAPID THERMAL PROCESSING, 1999, 99 (10): : 15 - 21
  • [48] Analytical subthreshold current modeling of nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a vertical gaussian doping profile
    Sufen Wei
    Guohe Zhang
    Huixiang Huang
    Jing Liu
    Zhibiao Shao
    Li Geng
    Cheng-Fu Yang
    Microsystem Technologies, 2018, 24 : 179 - 192
  • [49] Nanosecond laser annealing for phosphorous activation in ultra-thin implanted Silicon-On-Insulator substrates
    Alba, P. Acosta
    Kerdiles, S.
    Mathieu, B.
    Kachtouli, R.
    Besson, P.
    Veillerot, M.
    Aussenac, F.
    Fenouillet-Beranger, C.
    Mazzamuto, F.
    Toque-Tresonne, I.
    Huet, K.
    2016 21ST INTERNATIONAL CONFERENCE ON ION IMPLANTATION TECHNOLOGY (IIT), 2016,
  • [50] Hot-carrier degradation model for nanoscale ultra-thin body ultra-thin box SOI MOSFETs suitable for circuit simulators
    Karatsori, T. A.
    Theodorou, C. G.
    Haendler, S.
    Planes, N.
    Ghibaudo, G.
    Dimitriadis, C. A.
    MICROELECTRONIC ENGINEERING, 2016, 159 : 9 - 16