Clock Recovery Circuit Using a Transmission Line as a Delay Element from a 100Gb/s bit stream

被引：2

作者：

Kazi, Ibrahim ^{[1
]}

Reynaert, Patrick ^{[1
]}

Dehaene, Wim ^{[1
]}

机构：

[1] Katholieke Univ Leuven, Dept Elect Engn, Leuven, Belgium

来源：

2022 20TH IEEE INTERREGIONAL NEWCAS CONFERENCE (NEWCAS) | 2022年

关键词：

Slow Wave Transmission Line; Clock Recovery; High Speed Wireline; NRZ data; RECEIVER; NRZ;

D O I：

10.1109/NEWCAS52662.2022.9842073

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A phase rotator based architecture for clock recovery is presented for NRZ wireline links. A slow wave transmission line is used as a spatial buffer. The system is implemented in 40nm CMOS. It has a wide range of flexibility in recovering clocks continuously from 4GHz to 23GHz in presence of frequency offset between transmitter and receiver. The receiver can operate in different modes. In full rate mode the clock can be recovered up-till 23GHz which corresponds to a data rate of 23Gb/s. In the second mode a 1/8th rate clock of 12.5GHz is recovered in sub-sampling mode from a 100Gb/s bit stream. In the second mode, the full length of the transmission line is used as a very wide band delay element to generate multiple phase delayed versions of the input bit stream. The delayed versions of the input data are sampled by a single phase sampling clock. The concept of using a transmission line as a spatial buffer is proven.

引用

页码：261 / 264

页数：4

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