25-Gb/s Clock and Data Recovery IC Using Latch-Load Combined with CML Buffer Circuit for Delay Generation with 65-nm CMOS

被引：0

作者：

Tanaka, Tomonori ^{[1
]}

Furuichi, Kosuke ^{[1
]}

Uemura, Hiromu ^{[1
]}

Noguchi, Ryosuke ^{[1
]}

Koda, Natsuyuki ^{[1
]}

Arauchi, Koki ^{[1
]}

Omoto, Daichi ^{[1
]}

Inaba, Hiromi ^{[1
]}

Kishine, Keiji ^{[1
]}

Nakano, Shinsuke ^{[2
]}

Nogawa, Masafumi ^{[3
]}

Nosaka, Hideyuki ^{[2
]}

机构：

[1] Univ Shiga Prefecture, 2500 Hikone Hassaka, Hikone, Shiga 5228533, Japan

[2] NTT Corp, NTT Device Technol Labs, 3-1 Morinosato Wakamiya, Atsugi, Kanagawa 2430198, Japan

[3] NTT Corp, NTT Device Innovat Ctr, 3-1 Morinosato Wakamiya, Atsugi, Kanagawa 2430198, Japan

来源：

2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 25-Gb/s half-rate clock and data recovery (CDR) IC using a current-mode logic (CML) buffer circuit with a latch load circuit for delay generation is presented. To achieve low-power operation of the CDR, the latch-load circuit for delay generation is combined with a CND, buffer circuit, which provides a wide controllable delay range. This enable a reduction in the number of the CML circuits for delay generation used in the CDR IC. To confirm the validity of the proposed method, we fabricated a 25-Gb/s half-rate CDR IC with the 65-nm CMOS process. The power consumption of the proposed circuit is around half that of the conventional half-rate CDR circuit. The area for the core circuits is 0.09 mm(2), and the power consumption without output buffers is 96mW.

引用

页数：4

共 34 条

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