4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS

被引：1

作者：

Ito, Daisuke ^{[1
]}

Takahashi, Yasuhiro ^{[1
]}

Nakamura, Makoto ^{[1
]}

Inoue, Toshiyuki ^{[2
]}

Tsuchiya, Akira ^{[2
]}

Kishine, Keiji ^{[2
]}

机构：

[1] Gifu Univ, 1-1 Yanagido, Gifu, Gifu 5011193, Japan

[2] Univ Shiga Prefecture, 2500 Hassaka Cho, Hikone, Shiga 5228533, Japan

来源：

2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE, ISOCC | 2023年

关键词：

D O I：

10.1109/ISOCC59558.2023.10396067

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 4-channel 25-Gb/s VCSEL driver circuit in a 65nm CMOS with a small chip area and low power consumption is presented. The proposed circuit employs an inductor-less bandwidth enhancement based on feedback topology and an unbalanced current mode logic driver core to reduce power consumption. We designed and fabricated the proposed 4-channel driver circuit in a 65-nm CMOS technology. The proposed circuit achieves about half of the power consumption and chip area of the conventional one.

引用

页码：13 / 14

页数：2

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