A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion

Time-to-digital converters (TDCs) are promising building blocks for the digitalization of mixed-signal functionality in ultra-deep-submicron CMOS technologies. A short survey on state-of-the-art TDCs is given. A high-resolution TDC with low latency and low dead-time is proposed, where a coarse time quantization derived from a differential inverter delay-line is locally interpolated with passive voltage dividers. This high-resolution TDC is monotonic by construction which makes the concept very robust against process variations. The feasibility is demonstrated by a 90 nm demonstrator which uses a 4x interpolation and provides a time domain resolution of 4.7 ps. An integral nonlinearity of 1.2 LSB and a differential nonlinearity of 0.6 LSB are achieved. The resolution restrictions imposed by an uncertainty of the stop signal and local variations are derived theoretically.