A 8-bit MCU design using a four-pipeline architecture

被引：0
|
作者：
Lv, QL [1 ]
Li, P [1 ]
机构：
[1] Univ Elect Sci & Technol China, Inst Microelect, Chengdu 610054, Peoples R China
来源：
2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4 | 2002年
关键词：
MCU; CISC; IF(fetch instruction); ID (decode instruction); RO (read operands); WB (write back);
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
It is found that through improving the system architecture of PIC16C57's, the microcontroller's ( MCU) execution efficiency can be improved apparently. Two-pipeline architecture in PIC16C57 is replaced by a four-pipeline architecture. Experiment results verify that the designed MCU is compatible functionally with PIC16C57, its execution efficiency is 4 times as high as that of PIC16C57, its system clock reaches above 60MHz.
引用
收藏
页码：1462 / 1465
页数：4
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