An 8-bit 1Gsps CMOS pipeline ADC

An 8-bit 1Gsamples/s CMOS pipeline ADC(analog to digital converter) is designed with an open loop circuit design technique. To achieve the 1 GHz sampling rate, an interleaving technique is used. To get low power consumption and small die area, common blocks, such as, a reference string, bias blocks, interpolation amplifiers and pre-amplifiers in comparator are shared. At the 1GHz sampling rate, simulation results show that the power consumption is 400mW including digital logic with a power supply of 1.8V and the SNDR of 45dB with an input frequency of 207MHz. The proposed ADC was designed with 0.18um 6-Metal 1-Poly CMOS process and occupies an die area of 800um x 950um. The prototype device is now under fabrication.