Mobility enhancement in (110)-oriented ultra-thin-body single-gate and double-gate SOI MOSFETs

被引：0
|
作者：
Hiramoto, Toshiro [1 ]
Tsutsui, Gen [1 ]
Saitoh, Masurni [1 ]
Nagumo, Toshiharu [1 ]
Saraya, Takuya [1 ]
机构：
[1] Univ Tokyo, Inst Ind Sci, Meguro Ku, Tokyo 1538505, Japan
来源：
2006 INTERNATIONAL WORKSHOP ON NANO CMOS, PROCEEDINGS | 2006年
关键词：
quantum confinement; phonon scattering; surface roughness scattering; volume inversion;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Mobility enhancement of both electron and hole is experimentally demonstrated in (110) ultra-thin-body SOI MOVER Single-gate operation and double-gate operation are also compared Hole mobility enhancement in the single-gate operation is achieved by the suppression of phonon scattering, while electron mobility enhancement in double-gate operation is achieved by volume inversion. Based on the experimental results, the best device structure for highest CMOS circuit performance in future has been discussed.
引用
收藏
页码：44 / 55
页数：12
相关论文
共 50 条
  • [31] Transport in ultra-thin-body SOI and silicon nanowire MOSFETs
    Hiramoto, Toshiro
    Tsutsui, Gen
    Shimizu, Ken
    Kobayashi, Masaharu
    2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2, 2007, : 417 - 418
  • [32] Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultra-Thin Body nMOSFETs with SOI Thickness of Less Than 2 nm
    Shimizu, Ken
    Hiramoto, Toshiro
    2007 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 2007, : 125 - 126
  • [33] Hot-carrier effects in single- and double-gate thin-film SOI MOSFETs
    Jomaah, J.
    Balestra, F.
    Ghibaudo, G.
  • [34] Electron mobility and magneto transport study of ultra-thin channel double-gate Si MOSFETs
    Prunnila, M
    Ahopelto, J
    Gamiz, F
    SOLID-STATE ELECTRONICS, 2005, 49 (09) : 1516 - 1521
  • [35] ANALYTICAL MODELS FOR N(+)-P(+) DOUBLE-GATE SOI MOSFETS
    SUZUKI, K
    SUGII, T
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (11) : 1940 - 1948
  • [36] A simple modelling of device speed in double-gate SOI MOSFETs
    Rajendran, K
    Samudra, G
    MICROELECTRONICS JOURNAL, 2000, 31 (04) : 255 - 259
  • [37] Comparative analysis of the RF and noise performance of bulk and single-gate ultra-thin SOI MOSFETs by numerical simulation
    Eminente, S
    Alessandrini, M
    Fiegna, C
    SOLID-STATE ELECTRONICS, 2004, 48 (04) : 543 - 549
  • [38] Unified Quantum and Reliability Model for Ultra-Thin Double-Gate MOSFETs
    Rana Y. ElKashlan
    Omnia Samy
    Azza Anis
    Yehea Ismail
    Hamdy Abdelhamid
    Silicon, 2020, 12 : 21 - 28
  • [39] Unified Quantum and Reliability Model for Ultra-Thin Double-Gate MOSFETs
    ElKashlan, Rana Y.
    Samy, Omnia
    Anis, Azza
    Ismail, Yehea
    Abdelhamid, Hamdy
    SILICON, 2020, 12 (01) : 21 - 28
  • [40] Different Ground Plane (GP) Architectures on 25 nm Single-Gate (SG) versus Double-Gate (DG) UTBB SOI MOSFETs from Analog and RF Perspectives
    Othman, Noraini
    Arshad, M. K. Md
    Sabki, S. N.
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2017, 12 (04) : 392 - 399
12345