A systematic EHW approach to the evolutionary design of sequential circuits

被引:1
|
作者
Tao, Yanyun [1 ]
Zhang, Qing [3 ]
Zhang, Lijun [1 ]
Zhang, Yuzhen [2 ]
机构
[1] Soochow Univ, Sch Urban Rail Transportat, Suzhou 215137, Peoples R China
[2] Soochow Univ, Affiliated Hosp 1, Suzhou 215006, Peoples R China
[3] Shanghai Inst Technol, Sch Comp Sci & Informat Engn, Shanghai 201418, Peoples R China
关键词
Sequential circuit; State assignment; FSM; EHW method; Evolutionary strategy; Genetic programming; FINITE-STATE MACHINES; GENETIC ALGORITHM; LOGIC-CIRCUITS; ASSIGNMENT; OPTIMIZATION;
D O I
10.1007/s00500-015-1791-5
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
The main difficulty in the evolutionary design of finite state machines (FSMs) is lack of effective systematic EHW approach. To accomplish the evolutionary design of FSMs, a systematic EHW method named genetic programming-evolutionary strategy (GP-ES), which is a combination of ES and GP, is proposed. ES optimizes the state assignment and provide them to GP for population generation; GP is responsible for evolving the combinational part of FSM, and feeding the fitness of population back to ES for the evaluation of corresponding state assignments. GP-ES is tested extensively on twenty FSMs from MCNC Library. The results demonstrate that the GP-ES-derived state assignments are more efficient than the ones of Xia, Ali, Almaini and NOVA in the evolutionary design of FSMs. The results also illustrate that the GP-ES is superior to conventional synthesis tools in terms of complexity reduction for the design of small and middle FSMs. GP-ES also performs well in comparison with 3SD-ES in most cases.
引用
收藏
页码:5025 / 5038
页数:14
相关论文
共 50 条
  • [21] Evolutionary Design of Polymorphic Circuits with the Improved Evolutionary Repair
    Zhang, Xin
    Luo, Wenjian
    2013 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC), 2013, : 2192 - 2200
  • [22] Evolutionary Repair for Evolutionary Design of Combinational Logic Circuits
    Zhang, Xin
    Luo, Wenjian
    2012 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC), 2012,
  • [23] Transparent DFT: A design for testability and test generation approach for synchronous sequential circuits
    Pomeranz, Irith
    Reddy, Sudhakar M.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (06) : 1170 - 1175
  • [24] Design error diagnosis in sequential circuits
    Wahba, A
    Borrione, D
    CORRECT HARDWARE DESIGN AND VERIFICATION METHODS, 1995, 987 : 171 - 188
  • [25] DESIGN OF RELIABLE SYNCHRONOUS SEQUENTIAL CIRCUITS
    SAWIN, DH
    IEEE TRANSACTIONS ON COMPUTERS, 1975, C 24 (05) : 567 - 570
  • [26] Design of Ternary Reversible Sequential Circuits
    Khan, Mozammel H. A.
    2014 INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE), 2014, : 140 - 143
  • [27] Design of Testable Reversible Sequential Circuits
    Thapliyal, Himanshu
    Ranganathan, Nagarajan
    Kotiyal, Saurabh
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (07) : 1201 - 1209
  • [28] DESIGN FOR TESTABILITY OF SEQUENTIAL-CIRCUITS
    SUN, X
    LOMBARDI, F
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1994, 141 (03): : 153 - 160
  • [29] Survivable synchronous sequential circuits design
    Matrosova, A
    Andreeva, V
    BEC 2002: PROCEEDINGS OF THE 8TH BIENNIAL BALTIC ELECTRONIC CONFERENCE, 2002, : 133 - 136
  • [30] DESIGN OF ASYNCHRONOUS MULTILEVEL SEQUENTIAL CIRCUITS
    DUNCAN, FG
    ZISSOS, D
    PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON, 1972, 119 (02): : 133 - &