Low k1 logic design using gridded design rules

被引：17

作者：

Smayling, Michael C. ^{[1
]}

Liu, Hua-Yu ^{[2
]}

Cai, Lynn ^{[2
]}

机构：

[1] Tela Innovat Inc, 655 Technol Pkwy,Suite 150, Campbell, CA 95008 USA

[2] ASML Co, Brion Technol, Santa Clara, CA 95054 USA

来源：

DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION II | 2008年 / 6925卷

关键词：

low k(1); gridded design rules; restricted design rules; context dependent hotspots;

D O I：

10.1117/12.772875

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Dimensions for 32nm generation logic are expected to be similar to 45nm. Even with high NA scanners, the k(1) factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number. of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with "hotspot" prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela Canvas (TM) GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence. were also improved.

引用

页数：7

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