Hurdles in low k1 mass production

被引:0
|
作者
Yim, D [1 ]
Yang, HJ [1 ]
Park, C [1 ]
Hong, JK [1 ]
Choi, J [1 ]
机构
[1] Hynix Semicond Inc, Memory Res & Dev Div, Ichon 467701, Kyungki Do, South Korea
来源
关键词
low k1 mass production; definition of low kl; RET; optimum strategy;
D O I
10.1117/12.598625
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
As the optical lithography pushes toward its theoretical resolution limit 0.25k1, the application of aggressive Resolution Enhancement Techniques (RETs) are required in order to ensure necessary resolution, sufficient process window, and reasonable MEEF in critical layers. When chip makers are adopting RETs in low k1 device, there are a lot of crucial factors to take into account in the development and mass production. Those hurdles are not only difficult to overcome but also highly risky to the company, which adopts low k1 mass production strategy. But, low k1 production strategy is very attractive to all chip makers, owing to improving production capacity and cost of ownership. So, low k1 technology has been investigated by many lithography engineers. Lots of materials have been introduced. Most of them are just in RnD level. In this study, low k1 mass production issues shall be introduced., mainly. The definition of low k1 in mass production shall be suggested. And, a lot of low k1 issues shall be introduced, also. Most of them were investigated/experienced in RnD development stage and final mass production line. Low k1 mass production, is some what different from only RnD development.
引用
收藏
页码:813 / 820
页数:8
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