Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure

In this article, structure optimization of high-k interfacial layer (IL), depositedbetweenthe gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High-k IL can be formed during the high-k gate dielectric andmetal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high-k IL (T-hk) with gate length (LG), spacer length (Lext), and source/drain (S/D) length (LS/D), improved electrical performances were obtained. By optimizing T-hk with properly adjusted LG, Lext, and LS/D, highly saturated ON-/OFF-current ratio (ION/IOFF) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay (Cgg) properties and OFF-state leakage current were identified. In addition, the reason of increased OFF-state leakage, which can be shownwhenLext shrinkswith extending T-hk, was also investigated. Finally, the optimized electrical characteristics were obtained when T-hk is adjusted with LG and LS/D. The power was reduced about 27% with the same performance and 18% enhanced performancewas obtainedwhenT(hk) is optimized throughLG. On the contrary, reduced OFF-state leakage current and DIBL were confirmed in the case of optimization point with LS/D, which result in lower static power. Based on this comparison, optimization method and guideline for high-k IL was proposed.