An Efficient Diminished-1 Modulo 2n+1 Multiplier Using Signed-Digit Number Representation

被引：0

作者：

Tanaka, Yuuki ^{[1
]}

Wei, Shugang ^{[1
]}

机构：

[1] Gunma Univ, Fac Sci & Technol, Div Mech Sci & Technol, Gunma 3730057, Japan

来源：

TENCON 2015 - 2015 IEEE REGION 10 CONFERENCE | 2015年

关键词：

Modulo 2(n)+1 multipliers; diminished-1 number representation; residue number system; VLSI design;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose a new modulo 2(n) + 1 multiplier for the diminished-1 representation. Our algorithm generates inverted right perpendicularn/4inverted left perpendicular + 1 Signed-Digit( SD) numbers of n digits as the partial products and sums up these numbers by a multi-operand modulo 2(n) + 1 SD adder. We found that the proposed multiplier is smaller and faster than several proposed circuits.

引用

页数：6

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