Design and implementation of a new FPGA architecture

被引：2
|
作者：
Ma, XJ [1 ]
Tong, JR [1 ]
机构：
[1] Fudan Univ, Microelect Dept, ASIC & Syst State Key Lab, Shanghai 200433, Peoples R China
来源：
2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ICASIC.2003.1277335
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
FPGA is widely applied in datapath applications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDEGA (Field-programmable Datapath Enhanced Gate Array). The LC of FDEGA is optimized for datapath implementation. and can be programmed as either combinational or sequential device. FDEGA has hierarchical interconnection architecture. A chip with 16*16 LC array has been fabricated, and the design of LC and interconnection has been tested, and circuit sample chosen from practical digital system design has been implemented in FDEGA. The result proves that our design of FDEGA is correct.
引用
收藏
页码：816 / 819
页数：4
相关论文
共 50 条
  • [1] Design and Implementation of a Handshake Join Architecture on FPGA
    Oge, Yasin
    Miyoshi, Takefumi
    Kawashima, Hideyuki
    Yoshinaga, Tsutomu
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2012, E95D (12): : 2919 - 2927
  • [2] FPGA architecture design and toolset for logic implementation
    Tatas, K
    Siozios, K
    Vasiliadis, N
    Soudris, DJ
    Nikolaidis, S
    Siskos, S
    Thanailakis, A
    [J]. INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2003, 2799 : 607 - 616
  • [3] Design and Implementation of Hardware Architecture for Denoising Using FPGA
    Jeon, ByungMoo
    Lee, SangJun
    Jin, Jungdong
    Dung Duc Nguyen
    Jeon, Jae Wook
    [J]. 2013 IEEE 9TH INTERNATIONAL COLLOQUIUM ON SIGNAL PROCESSING AND ITS APPLICATIONS (CSPA), 2013, : 83 - 88
  • [4] Scalable Pipelined CORDIC Architecture Design and Implementation in FPGA
    Adiono, Trio
    Purba, Randy Saut
    [J]. 2009 INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING AND INFORMATICS, VOLS 1 AND 2, 2009, : 628 - 631
  • [5] Design and implementation of Galaxian game based on FPGA Architecture
    Liu Changhua
    Xu Xiaole
    Ding Guodong
    [J]. MECHANICAL DESIGN AND POWER ENGINEERING, PTS 1 AND 2, 2014, 490-491 : 1047 - 1052
  • [6] Design and implementation of a new architecture of a real-time reconfigurable digital modulator on FPGA
    Andre, W.
    Couillard, O.
    [J]. ELECTRONICS LETTERS, 2018, 54 (18) : 1094 - 1095
  • [7] Design and implementation of FPGA based communication architecture for control system
    Zhang, An-Kun
    Wang, Wei-Min
    Hu, Xie-He
    Huang, Wen-Jun
    [J]. Zhejiang Daxue Xuebao(Gongxue Ban)/Journal of Zhejiang University (Engineering Science), 2010, 44 (04): : 659 - 664
  • [8] Design and Implementation of Fast FPGA Based Architecture for Reversible Watermarking
    Ghosh, Sudip
    Kundu, Buoy
    Datta, Debopam
    Maity, Santi P.
    Rahaman, Hafizur
    [J]. 2013 INTERNATIONAL CONFERENCE ON ELECTRICAL INFORMATION AND COMMUNICATION TECHNOLOGY (EICT), 2013,
  • [9] Implementation of FPGA design of FFT architecture based on CORDIC algorithm
    Inguva, Sharath Chandra
    Seventiline, J. B.
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 2021, 108 (11) : 1914 - 1939
  • [10] Modified FPGA based Design and Implementation of Reconfigurable FFT Architecture
    Bhakthavatchalu, Ramesh
    Kripalal, Ammu
    Nair, Suchitra
    Venugopal, Pallavi
    Viswanath, Meera
    [J]. 2013 IEEE INTERNATIONAL MULTI CONFERENCE ON AUTOMATION, COMPUTING, COMMUNICATION, CONTROL AND COMPRESSED SENSING (IMAC4S), 2013, : 818 - 822
12345