Design and implementation of a new FPGA architecture

被引:2
|
作者
Ma, XJ [1 ]
Tong, JR [1 ]
机构
[1] Fudan Univ, Microelect Dept, ASIC & Syst State Key Lab, Shanghai 200433, Peoples R China
关键词
D O I
10.1109/ICASIC.2003.1277335
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
FPGA is widely applied in datapath applications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDEGA (Field-programmable Datapath Enhanced Gate Array). The LC of FDEGA is optimized for datapath implementation. and can be programmed as either combinational or sequential device. FDEGA has hierarchical interconnection architecture. A chip with 16*16 LC array has been fabricated, and the design of LC and interconnection has been tested, and circuit sample chosen from practical digital system design has been implemented in FDEGA. The result proves that our design of FDEGA is correct.
引用
收藏
页码:816 / 819
页数:4
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