共 50 条
- [34] Low-damage gate etching with high degree of anisotropy in high-density DRAM cell JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2002, 41 (4B): : 2380 - 2384
- [35] Low temperature PZT ferroelectric capacitor process for high density capacitor-over-interconnect (COI) FeRAM application SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 692 - 695
- [36] A novel stack capacitor cell for high density FeRAM compatible with CMOS logic INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 543 - 546
- [37] Minority Carrier Disturb in Thyristor Memory Arrays and a Novel Cell Design for High Density DRAM 2017 IEEE 9TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2017, : 56 - 59
- [38] Fully planarized stacked capacitor cell with deep and high aspect ratio contact hole for Giga-bit DRAM 1997 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1997, : 21 - 22
- [40] Highly scalable sub-10F2 ITIC COB cell for high density FRAM 2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2001, : 111 - 112