An illustration of 90nm CMOS layout on PC

被引：0

作者：

Sicard, E ^{[1
]}

Ben Dhia, S ^{[1
]}

机构：

[1] DGEI, INSA, F-31077 Toulouse, France

来源：

ICCDCS 2004: Fifth International Caracas Conference on Devices, Circuits and Systems | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The 90nm CMOS process technology, in commercial production in 2004, includes copper interconnects, 6 to 12 metal layers and 5-10 types of MOS devices. In co-operation with ST-microelectronics, the layout editor/simulator MICROWIND has been configured to support this state-of-the art CMOS process for research and training purpose. This paper describes the recent developments and their application to microelectronics training.

引用

页码：315 / 318

页数：4

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