Multiplexer implementation of low-complexity polynomial basis multiplier in GF(2m) using all one polynomial

被引：4

作者：

Chiou, Che Wun ^{[1
]}

Lee, Chiou-Yng ^{[2
]}

Yeh, Yun-Chi ^{[3
]}

机构：

[1] Ching Yun Univ, Dept Comp Sci & Informat Engn, Chungli 320, Taiwan

[2] Lunghwa Univ Sci & Technol, Dept Comp Informat & Network Engn, Tao Yuan 333, Taiwan

[3] Ching Yun Univ, Dept Elect Engn, Jhongli 320, Taiwan

来源：

INFORMATION PROCESSING LETTERS | 2011年 / 111卷 / 21-22期

关键词：

Multiplier; Cryptography; Multiplexer; Finite field; Polynomial basis; FINITE-FIELD MULTIPLIER; PARALLEL MULTIPLIERS; CONSTRUCTION;

D O I：

10.1016/j.ipl.2011.08.004

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Polynomial basis multipliers are realized by conventional AND and XOR gates. In this study, polynomial basis multiplier is implemented by multiplexers rather than traditional AND and XOR gates. Two bits are processed at the same time. The proposed multiplexer-based multiplier saves about 14% space complexity as compared to other existing multipliers. Furthermore, the proposed multiplier also saves about 37% time complexity (for example, m = 156) while comparing with other existing multipliers. (C) 2011 Elsevier B.V. All rights reserved.

引用

页码：1044 / 1047

页数：4

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