Positive Gate Bias and Temperature-Induced Instability of α-InGaZnO Thin-Film Transistor With ZrLaO Gate Dielectric

The effects of positive gate-bias stress (PGBS) and temperature on the electrical instability of amorphous InGaZnO thin-film transistor with a thin ZrLaO film as gate dielectric were investigated. An abnormal negative PGBS-induced V-th shift (Delta V-th, up to -3.3 V) without subthreshold swing (SS) degradation was found at 300 K, while a positive PGBS-induced Delta V-th (+ 1.0 V at 250 K and + 0.7 V at 200 K) without SS degradation appeared at low temperature. The negative PGBS-induced Delta V-th at 300 K is due to carrier creation in the InGaZnO film, which is mainly resulted from the enhanced control ability of the gate on the channel by using thin high-k ZrLaO as the gate dielectric of the transistor. The positive PGBS-induced Delta V-th at low temperature is caused by electron trapping happening near the ZrLaO/InGaZnO interface at low temperature.