Effects of Thermal Annealing on La2O3 Gate Dielectric of InGaZnO Thin-Film Transistor

被引:6
|
作者
Huang, X. D. [1 ]
Song, J. Q. [2 ]
Lai, P. T. [2 ]
机构
[1] Southeast Univ, Minist Educ, Key Lab MEMS, Nanjing 210096, Jiangsu, Peoples R China
[2] Univ Hong Kong, Dept Elect & Elect Engn, Hong Kong, Hong Kong, Peoples R China
关键词
Surface roughness - Zinc compounds - Thin film circuits - Gallium compounds - Grain boundaries - Annealing - Gate dielectrics - Thin films - Indium compounds - Lanthanum oxides - Threshold voltage;
D O I
10.1149/2.0011509ssl
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor (TFT) are investigated by varying annealing temperature. Due to densification and enhanced moisture resistance of the La2O3 film, its surface roughness and interface with InGaZnO are improved by the thermal annealing, thus leading to significant improvement in the TFT electrical performance. However, higher-temperature (450 degrees C) annealing deteriorates the dielectric roughness and induces more traps associated with grain boundaries in the La2O3 film. The TFT with an appropriate annealing (350 degrees C) shows the best performance with smallest subthreshold swing (0.276 V/dec), lowest threshold voltage (3.01 V), highest field-effect mobility (23.2 cm(2)/V.s) and largest on-off current ratio (3.52 x 10(8)). (C) 2015 The Electrochemical Society. All rights reserved.
引用
收藏
页码:Q44 / Q46
页数:3
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