Selective Thinning Technology of Solder Resist for Ultra-Thin and High-Density IC Packaging

This paper presents an innovative process technology in solder resist (SR) thinning to form multi-stepped SR structures. The resist thinning (RT) process can thin down SR layer highly uniformly at a large panel scale. The RT process is also capable of SR patterning by combined with photolithography process to enable selective SR thinning. This paper first discusses the process mechanism and studies impact of process parameters. Comparison studies of the RT process against a standard development process were conducted to demonstrate uniform SR thickness reduction by the RT process. Additionally, variety of unique SR structures were demonstrated using the RT process to illustrate potential applications of the process to variety of packaging substrates, such as ultra-thin substrates, high-density substrates, and multi-chip module substrates.