Selective Thinning Technology of Solder Resist for Ultra-Thin and High-Density IC Packaging

被引：1

作者：

Suzuki, Yuya ^{[1
]}

Toyoda, Yuji ^{[2
]}

机构：

[1] Taiyo Amer, 1731 Technol Dr,Ste 595, San Jose, CA 95110 USA

[2] Mitsubishi Paper Mills Co Ltd, Sumida Ku, 2-10-14 Ryogoku, Tokyo, Japan

来源：

IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021) | 2021年

关键词：

Solder resist thinning; Wet etching; Multi-stepped structure; Half-etching; Patterning; PERFORMANCE;

D O I：

10.1109/ECTC32696.2021.00133

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an innovative process technology in solder resist (SR) thinning to form multi-stepped SR structures. The resist thinning (RT) process can thin down SR layer highly uniformly at a large panel scale. The RT process is also capable of SR patterning by combined with photolithography process to enable selective SR thinning. This paper first discusses the process mechanism and studies impact of process parameters. Comparison studies of the RT process against a standard development process were conducted to demonstrate uniform SR thickness reduction by the RT process. Additionally, variety of unique SR structures were demonstrated using the RT process to illustrate potential applications of the process to variety of packaging substrates, such as ultra-thin substrates, high-density substrates, and multi-chip module substrates.

引用

页码：774 / 780

页数：7

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