A new low power high performance flip-flop

被引:0
|
作者
Sayed, Ahmed [1 ]
Al-Asaad, Hussain [1 ]
机构
[1] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Low power flip-flops are crucial for the design of low-power digital systems. In this paper we delve into the details of flip-flop design and optimization for low power We compare the lowest power flip-flops reported in the literature and introduce a new flip-flop that competes with them.
引用
收藏
页码:723 / +
页数:2
相关论文
共 50 条
  • [41] Design and Implementation of Embedded Logic Flip-Flop for Low Power Applications
    Sudheer, A.
    Ravindran, Ajith
    [J]. PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES, ICICT 2014, 2015, 46 : 1393 - 1400
  • [42] Low Power Magnetic Flip-Flop Optimization With FDSOI Technology Boost
    Cai, Hao
    Wang, You
    Naviner, Lirida Alves de Barros
    Zhao, Weisheng
    [J]. IEEE TRANSACTIONS ON MAGNETICS, 2016, 52 (08)
  • [43] Low Power Conditional Pulse Control with Transmission Gate Flip-Flop
    Berwal, Deepak
    Kumar, Ashish
    Kumar, Yogendera
    [J]. 2015 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION & AUTOMATION (ICCCA), 2015, : 1358 - 1362
  • [44] Low power flip-flop with clock gating on master and slave latches
    Strollo, AGM
    De Caro, D
    [J]. ELECTRONICS LETTERS, 2000, 36 (04) : 294 - 295
  • [45] Ultra-Low Power NAND Based Multiplexer And Flip-Flop
    Varun, Ishan
    Gupta, Tarun Kumar
    [J]. 2013 4TH NIRMA UNIVERSITY INTERNATIONAL CONFERENCE ON ENGINEERING (NUICONE 2013), 2013,
  • [46] A novel low power flip-flop design using footless scheme
    Lin, Jin-Fa
    Tsai, Ming-Yan
    Chang, Ching-Sheng
    Tsai, Yu-Ming
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2018, 97 (02) : 365 - 370
  • [47] On the computational power of flip-flop proteins on membranes
    Krishna, Shankara Narayanan
    [J]. Computation and Logic in the Real World, Proceedings, 2007, 4497 : 695 - 704
  • [48] A Novel High Performance Scan Architecture with Dmuxed Scan Flip-Flop (DSF) for Low Shift Power Scan Testing
    Kim, Jung-Tae
    Kim, Insoo
    Lee, Keon-Ho
    Kim, Yong-Hyun
    Baek, Chul-Ki
    Lee, Kyu-Taek
    Min, Hyoung Bok
    [J]. JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY, 2009, 4 (04) : 559 - 565
  • [49] A New CMOS Ultra Low Power Flip-Flop Circuit with a Minimization of Internal Node Transitions
    Lee, Suhyenn
    Kam, Gyuwon
    Yoon, Seungjoo
    Kim, Soo Youn
    Song, Minkyu
    [J]. 2022 37TH INTERNATIONAL TECHNICAL CONFERENCE ON CIRCUITS/SYSTEMS, COMPUTERS AND COMMUNICATIONS (ITC-CSCC 2022), 2022, : 505 - 506
  • [50] High-Performance Low-Power Magnetic Tunnel Junction Based Non-Volatile Flip-Flop
    Na, Taehui
    Ryu, Kyungho
    Kim, Jisu
    Jung, Seong-Ook
    Kim, Jung Pill
    Kang, Seung H.
    [J]. 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 1953 - 1956