Design of a Low-Voltage EEG Detector Based on a Chopping Amplifier in CMOS 65-nm

被引：0

作者：

Seutin, Nathan ^{[1
]}

Garcia-Vazquez, Hugo ^{[1
]}

Quenon, Alexandre ^{[1
]}

Dualibe, Fortunato Carlos ^{[1
]}

机构：

[1] Univ Mons UMONS, Elect & Microelect Unit, Blvd Dolez 31, B-7000 Mons, Belgium

来源：

2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2018年

关键词：

EEG detector; CMOS; 65nm; g(m)/I-D; Gm-C; Filter; Chopping Amplifier; Fully Differential; OA; OTA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a design of an Electroencephalography (EEG) detector circuit powered by 1.2V using a CMOS 65-nm process. The circuit comprises two main blocks: a chopping amplifier and a bandpass filter bank. The latter was implemented using Gm-C technology. The chopping amplifier comprises two Miller amplifiers and two choppers. The gm/I-D methodology is used in order to size transistors. The designed EEG detector can amplify brain signals in the order of microvolts by 100dB. The whole detector demands a current consumption of 543RA and 3116 mu m(2) of active area. The power supply rejection PSRR results in 130.05dB. The circuit can be used in a Brain Computer Interface (BCI) for several applications.

引用

页码：261 / 264

页数：4

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