An Ultra Low-Voltage Standard Cell Library in 65-nm CMOS Process Technology

被引：0

作者：

Peje, Joseph Leandro B. ^{[1
]}

Ho, Hani Herbert L. ^{[1
]}

Barot, Floro, Jr. ^{[1
]}

Bautista, Maria Fe G. ^{[1
]}

Misagal, Carl Christian E. ^{[1
]}

Hizon, John Richard E. ^{[1
]}

Alarcon, Louis P. ^{[1
]}

机构：

[1] Univ Philippines Diliman, Elect & Elect Engn Inst, Microelect & Microproc Lab, Quezon City 1101, Philippines

来源：

TENCON 2014 - 2014 IEEE REGION 10 CONFERENCE | 2014年

关键词：

low-power; standard cell library; sensor platform; subthreshold;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the design of an ultra-low voltage standard cell library is discussed. This includes the design constraints in designing each gate on a schematic level as well as techniques used in designing the layout. The method of performing timing and power characterization of the standard cell library and how the logical and physical library files are generated are discussed. The accuracy of the standard cell library is then verified through the use of several test circuits.

引用

页数：6

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