A 60 GHz High Gain Transformer-Coupled Differential Cascode Power Amplifier in 65 nm CMOS

A fully differential high gain V-band three-stage transformer-coupled power amplifier (PA) is designed and implemented in 65 nm CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanism, single-ended to differential conversion, and input/inter-stage/output matching are used to facilitate a compact amplifier design. The design and optimization methodologies of active and passive devices are presented. With a cascode configuration, the amplifier achieves a linear gain of 30.5 dB centered at 63.5 GHz and a -40 dB reverse isolation under a 1 V supply, which compares favorably to recent published V-band PAs. The amplifier delivers 9 dBm and 13 dBm saturation output power (P-sat) under 1 V and 1.5 V supplies, respectively, and occupies score chip area of 0.05 mm(2). The measurement results validate a high gain and area-efficient power amplifier design methodology in deep-scaled CMOS for applications in millimeter-wave communication.