Development of a sub-nanosecond time-to-digital converter based on a field-programmable gate array

被引：4

作者：

Sano, Y. ^{[1
]}

Tomoto, M. ^{[1
]}

Horii, Y. ^{[1
]}

Sasaki, O. ^{[2
]}

Uchida, T. ^{[2
]}

Ikeno, M. ^{[2
]}

机构：

[1] Nagoya Univ, Nagoya, Aichi 4648601, Japan

[2] High Energy Accelerator Res Org, KEK, Tsukuba, Ibaraki, Japan

来源：

JOURNAL OF INSTRUMENTATION | 2016年 / 11卷

关键词：

Front-end electronics for detector readout; Particle tracking detectors (Gaseous detectors);

D O I：

10.1088/1748-0221/11/03/C03053

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

The present time-to-digital converter (TDC) chips for the monitored drift tube (MDT) chambers at the ATLAS experiment will be replaced with new ones for the High-Luminosity LHC, expected to begin operation in 2026. The design and the performance of a 24 channel TDC with a variable time binning of down to 0.28 nsec based on a Xilinx Kintex-7 field programmable gate array are reported. The time measurement is provided by a multisampling scheme with quad phase clocks synchronized with an external reference clock. The differential and integral nonlinearities have been measured to be less than half of the time binning. The temperature dependence on the performance is observed to be small. In conclusion the obtained performance of the time measurement is sufficiently high for the use with MDT chambers.

引用

页数：7

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