Through wafer interconnection technologies for advanced electronic devices

被引:0
|
作者
de Samber, M [1 ]
Nellissen, T [1 ]
van Grunsven, E [1 ]
机构
[1] Philips Ctr Ind Technol, NL-5600 MD Eindhoven, Netherlands
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
There is a need for miniaturizing electronic components such as ICs and modules that are used in portable devices like cellular phones and PDAs. Miniaturization not only results in a reduced foot print of the components on the printed board but it can also have a positive effect on the device performance. The ultimate miniaturization is reached when packaging the component into a Chip Size Package (CSP). To enable this the bonding pads of ICs can be rerouted into, e.g., a Ball Grid Array (BGA) configuration. For devices such as vertical discrete components and stacked dies planar rerouting is not sufficient. Introducing so-called through wafer interconnect enables addressing the back side and so these devices can be converted into CSPs. Although through wafer interconnect requires rather complicated technologies, wafer level processing (resulting in simultaneous fabrication of large number of packages) limits the additional packaging cost.
引用
收藏
页码:1 / 6
页数:6
相关论文
共 50 条
  • [1] Advanced Electronic Interconnection
    Lin, Shih-Kang
    [J]. JOM, 2019, 71 (09) : 2996 - 2997
  • [2] Advanced Electronic Interconnection
    Shih-kang Lin
    [J]. JOM, 2019, 71 : 2996 - 2997
  • [3] MATERIAL AND PROCESSING TECHNOLOGIES OF POLYIMIDE FOR ADVANCED ELECTRONIC DEVICES
    ENDO, A
    TAKADA, M
    TAKASAGO, H
    SUGIURA, T
    YADA, T
    ONISHI, Y
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1986, 133 (08) : C314 - C314
  • [4] MATERIAL AND PROCESSING TECHNOLOGIES OF POLYIMIDE FOR ADVANCED ELECTRONIC DEVICES
    ENDO, A
    TAKADA, M
    ADACHI, K
    TAKASAGO, H
    YADA, T
    ONISHI, Y
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1987, 134 (10) : 2522 - 2527
  • [5] Applications of advanced materials technologies to vacuum electronic devices
    Calame, JP
    Abe, DK
    [J]. PROCEEDINGS OF THE IEEE, 1999, 87 (05) : 840 - 864
  • [6] Through Mold Interconnection assessment for advanced Fan Out Wafer Level Packaging applications
    Plihon, Aurelia
    Deschaseaux, Edouard
    Franiatte, Remi
    Argoux, Maxime
    Dechamp, Jerome
    Guillaume, Jennifer
    Charbonnier, Jean
    [J]. 2020 IEEE 8TH ELECTRONICS SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2020,
  • [7] ELECTRICAL INTERCONNECTION THROUGH SILICON-WAFER
    DUPEUX, T
    SIBUET, H
    DAUPHIN, PD
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1988, 135 (08) : C359 - C359
  • [8] Scalable Through Molding Interconnection realization for advanced Fan Out Wafer Level Packaging applications
    Plihon, Aurelia
    Deschaseaux, Edouard
    Franiatte, Remi
    Dechamp, Jerome
    Vaudaine, Simon
    Guillaume, Jennifer
    Brunet-Manquat, Catherine
    Moreau, Stephane
    Coudrain, Perceval
    [J]. IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022), 2022, : 2122 - 2127
  • [9] A Wafer-Level Vacuum Package Using Glass-Reflowed Silicon Through-Wafer Interconnection for Nano/Micro Devices
    Jin, Joo-Young
    Yoo, Seung-Hyun
    Yoo, Byung-Wook
    Kim, Yong-Kweon
    [J]. JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2012, 12 (07) : 5252 - 5262
  • [10] Wafer probing technologies require unique devices
    Scharrer, C
    [J]. R&D MAGAZINE, 2002, 44 (12): : 59 - 60