A Low-Power Single-Phase Clock Multiband Flexible Divider

被引：35

作者：

Manthena, Vamshi Krishna ^{[1
]}

Manh Anh Do ^{[1
]}

Boon, Chirn Chye ^{[1
]}

Yeo, Kiat Seng ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Circuits & Syst, Singapore 639798, Singapore

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2012年 / 20卷 / 02期

关键词：

DFF; dual modulus prescaler; dynamic logic; E-TSPC; frequency synthesizer; high-speed digital circuits; true single-phase clock (TSPC); wireless LAN (WLAN); CMOS FREQUENCY-SYNTHESIZER;

D O I：

10.1109/TVLSI.2010.2100052

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-mu m CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.

引用

页码：376 / 380

页数：5

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