共 50 条
- [1] An accurate design approach for two-stage CMOS operational amplifiers [J]. 2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2016, : 563 - 566
- [4] Design guidelines for two-stage cascode-compensated operational amplifiers [J]. 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, : 264 - +
- [6] An offset cancellation technique for two-stage CMOS operational amplifiers [J]. 2007 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2007, : 154 - +
- [7] Hybrid cascode compensation for two-stage cmos operational amplifiers [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1565 - 1568
- [8] Fast-settling CMOS two-stage operational transconductance amplifiers and their systematic design [J]. 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS, 2002, : 839 - 842
- [10] A new compensation technique for two-stage CMOS operational transconductance amplifiers [J]. ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 539 - 542