Loop Latency Reduction Technique for All-Digital Clock and Data Recovery Circuits

This paper presents an all-digital implemented clock and data recovery circuit. To alleviate the instability contributed by the large latency of digital loop filter, the architecture of two integral paths is proposed in this work. The loop latency from the digital loop filter can be removing by introducing a high speed pre-accumulator cascaded by a low speed accumulator. It increases the phase margin and also improves the loop stability. A smaller proportional gain for the digital loop filter can be chosen without sacrificing the stability. Hence the jitter performance can be improved. The experimental chip occupies a chip area of 0.432mm2 in standard 0.18 square m CMOS technology. It consumes 23.4mW from a 1.8V supply and achieves a peak-to-peak jitter of 0.064 unit interval while operating at the bit rate of 1.25Gb/s.