Fast power loss calculation for digital static CMOS circuits

被引：3
|
作者：
Gavrilov, S
Glebov, A
Rusakov, S
Blaauw, D
Jones, L
Vijayan, G
机构：
来源：
EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/EDTC.1997.582392
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present a new dynamic power estimation method that produces accurate power measures at considerably faster run rimes. The approach uses an enhanced switch-level simulation algorithm that takes into account both short-circuit power and charge-sharing power effects. In benchmarks against a popular commercial power simulation tool, our approach yields power measurements on average within 3% of the commercial solution, while taking between 15 to 20 times less CPU time.
引用
收藏
页码：411 / 415
页数：5
相关论文
共 50 条
  • [41] Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout
    Ruiz, J. M.
    Fernandez-Garcia, R.
    Gil, I.
    Morata, M.
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2012, 28 (06): : 865 - 868
  • [42] Efficiency of body biasing in 90 nm CMOS for low power digital circuits
    von Arnim, K
    Borinski, E
    Seegebrecht, P
    Fiedler, H
    Brederlow, R
    Thewes, R
    Berthold, J
    Pacha, C
    ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2004, : 175 - 178
  • [43] Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout
    J. M. Ruiz
    R. Fernández-Garcia
    I. Gil
    M. Morata
    Journal of Electronic Testing, 2012, 28 : 865 - 868
  • [44] Average and Maximum Power Consumption of Digital CMOS Circuits Using Logic Pictures
    Fouda, M. F.
    Abdelhalim, M. B.
    Amer, H. H.
    2009 INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING AND SYSTEMS (ICCES 2009), 2009, : 225 - +
  • [45] CMOS DIGITAL CIRCUITS CONTROL HIGH-POWER AC LOADS DIRECTLY
    不详
    CONTROL ENGINEERING, 1976, 23 (03) : 26 - 26
  • [46] Application of adaptive evolutionary algorithm for low power design of CMOS digital circuits
    Koziel, S
    Szczesniak, W
    ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 685 - 688
  • [47] Digital neurons and arithmetic CMOS circuits
    Pedroni, VA
    IC-AI'2001: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE, VOLS I-III, 2001, : 1321 - 1327
  • [48] NOISE IN DIGITAL DYNAMIC CMOS CIRCUITS
    LARSSON, P
    SVENSSON, C
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (06) : 655 - 662
  • [49] An optimization-based error calculation for statistical power estimation of CMOS logic circuits
    Kwak, B
    Park, ES
    1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 690 - 693
  • [50] SIGNAL DELAY CALCULATION FOR INTEGRATED CMOS CIRCUITS
    HUSS, SA
    GERBERSHAGEN, M
    AEU-ARCHIV FUR ELEKTRONIK UND UBERTRAGUNGSTECHNIK-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 1987, 41 (04): : 214 - 222
12345