Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout

被引：0

作者：

J. M. Ruiz

R. Fernández-Garcia

I. Gil

M. Morata

机构：

[1] Escuela Universitaria Salesiana de Sarriá,Department of Electronics Engineering

[2] UPC Barcelona Tech,undefined

来源：

Journal of Electronic Testing | 2012年 / 28卷

关键词：

MOSFET; Electromagnetic compatibility; Electrical modeling; Simultaneous switching noise;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

In this paper the power consumption and power integrity of a CMOS ring oscillator has been analysed when their pFETs are subjected to negative bias temperature instability (NBTI). The impact of pFET under NBTI has been experimentally quantified whereas CMOS ring oscillator power consumption and power integrity have been evaluated by means of electrical full-model simulation. The results show that power consumption is reduced and power integrity remains constant with NBTI wearout..

引用

页码：865 / 868

页数：3

共 50 条

[1] Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout
Ruiz, J. M.
Fernandez-Garcia, R.
Gil, I.
Morata, M.
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2012, 28 (06): : 865 - 868
[2] MINIMIZING POWER-CONSUMPTION IN DIGITAL CMOS CIRCUITS
CHANDRAKASAN, AP
BRODERSEN, RW
[J]. PROCEEDINGS OF THE IEEE, 1995, 83 (04) : 498 - 523
[3] Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
Butzen, Paulo F.
da Rosa, Leomar S., Jr.
Chiappetta Filho, Erasmo J. D.
Reis, Andre I.
Ribas, Renato P.
[J]. MICROELECTRONICS JOURNAL, 2010, 41 (04) : 247 - 255
[4] DVTS APPROACH TO DIGITAL CMOS CIRCUITS FOR DECREASING TOTAL POWER CONSUMPTION
Archanadevi, C.
Prabhu, V.
[J]. 2013 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2013, : 1203 - 1207
[5] Impact of NBTI on the Performance of 35nm CMOS Digital Circuits
Wang, Yangang
Zwolinski, M.
[J]. 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 440 - 443
[6] Average and Maximum Power Consumption of Digital CMOS Circuits Using Logic Pictures
Fouda, M. F.
Abdelhalim, M. B.
Amer, H. H.
[J]. 2009 INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING AND SYSTEMS (ICCES 2009), 2009, : 225 - +
[7] Technique for reducing power consumption in CMOS circuits
Girard, P
Landrault, C
Pravossoudovitch, S
Severac, D
[J]. ELECTRONICS LETTERS, 1997, 33 (06) : 485 - 486
[8] Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits
Alvandpour, A
Larsson-Edefors, P
Svensson, C
[J]. 1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, 1998, : 245 - 249
[9] On maximum current estimation in CMOS digital circuits
Ciuplys, D
Larsson-Edefors, P
[J]. 17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 658 - 661
[10] Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption
Dhillon, Yuvraj Singh
Diril, Abdulkadir Utku
Chatterjee, Abhijit
[J]. JOURNAL OF LOW POWER ELECTRONICS, 2007, 3 (01) : 78 - 95

← 1 2 3 4 5 →