System-level State Equality Detection for the Formal Dynamic Verification of Legacy Distributed Applications

被引:1
|
作者
Guthmuller, Marion [1 ,2 ,3 ]
Quinson, Martin [1 ,2 ,3 ]
Corona, Gabriel [1 ,2 ,3 ]
机构
[1] Univ Lorraine, LORIA, UMR 7503, Vandoeuvre Les Nancy, France
[2] CNRS, LORIA, UMR 7503, Vandoeuvre Les Nancy, France
[3] Inria, AlGorille Project Team, Villers Les Nancy, France
关键词
D O I
10.1109/PDP.2015.95
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The ever increasing complexity of distributed systems mandates to formally verify their design and implementation. Unfortunately, the common approaches and existing tools to formally establish the correctness of these systems remain hardly applicable to the kind of legacy applications that are commonly found in the HPC community. We present how system-level memory introspection can be achieved directly at runtime without relying on the source code analysis. We use this mechanism to detect the equality of the application's state at system level. As the storage of the system state may be memory expensive, we compact the memory by sharing unchanged memory pages between snapshots. This enables the automated verification of safety and liveness properties on legacy distributed applications written in Fortran or C/C++ using the MPI standard. We demonstrate the effectiveness of our approach on several programs from the MPICH3 test suite.
引用
收藏
页码:451 / 458
页数:8
相关论文
共 50 条
  • [31] System-level dynamic power management
    Benini, L
    Bogliolo, A
    De Micheli, G
    IEEE ALESSANDRO VOLTA MEMORIAL WORKSHOP ON LOW-POWER DESIGN, PROCEEDINGS, 1999, : 23 - 31
  • [32] Tracing system-level communication in distributed systems
    Mann, ZA
    Kondorosi, K
    SOFTWARE-PRACTICE & EXPERIENCE, 2004, 34 (08): : 727 - 755
  • [33] Challenges in using system-level models for RTL verification
    Ng, Kelvin
    2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 812 - 815
  • [34] Synchronization verification in system-level design with ILP solvers
    Sakunkonchak, T
    Komatsu, S
    Fujita, M
    THIRD ACM & IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CO-DESIGN, PROCEEDINGS, 2005, : 121 - 130
  • [35] Synchronization verification in system-level design with ILP solvers
    Sakunkonchak, Thanyapat
    Komatsu, Satoshi
    Fujita, Masahiro
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2006, E89A (12) : 3387 - 3396
  • [36] System-Level Verification of Embedded Operating Systems Components
    Ludwich, Mateus Krepsky
    Froehlich, Antonio Augusto
    2012 BRAZILIAN SYMPOSIUM ON COMPUTING SYSTEM ENGINEERING (SBESC 2012), 2012, : 161 - 165
  • [37] Assertion-Based Verification for System-Level Designs
    Sohofi, Hassan
    Navabi, Zainalabedin
    PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014), 2015, : 582 - 588
  • [38] Simulator Semantics for System Level Formal Verification
    Mancini, Toni
    Mari, Federico
    Massini, Annalisa
    Melatti, Igor
    Tronci, Enrico
    ELECTRONIC PROCEEDINGS IN THEORETICAL COMPUTER SCIENCE, 2015, (193): : 86 - 99
  • [39] SyLVaaS: System Level Formal Verification as a Service
    Mancini, Toni
    Mari, Federico
    Massini, Annalisa
    Melatti, Igor
    Tronci, Enrico
    23RD EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP 2015), 2015, : 476 - 483
  • [40] Deriving process networks from weakly dynamic applications in system-level design
    Stefanov, T
    Deprettere, E
    CODES(PLUS)ISSS 2003: FIRST IEEE/ACM/IFIP INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN & SYSTEM SYNTHESIS, 2003, : 90 - 96